The present invention relates generally to semiconductor devices and more specifically to a method and system for eliminating the number of voids in semiconductor devices.
Semiconductor manufacturers have increasingly turned to high density Metal Oxide Semiconductor (MOS) arrays in their integrated circuit design schemes. To achieve a high density integrated circuit, features such as metal-oxide semiconductor field-effect transistors (MOSFETs) must be as small as possible. Typically, high density flash memory integrated circuits utilize NAND-type gates as opposed to NOR-type gates since NAND gates have a considerably higher density than NOR gates. Smaller transistors allow more transistors to be placed on a single substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area. FIG. 1 illustrates a cross section of two conventional MOSFET cells. The cells 100 and 150 are comprised of gate stacks 102, 106 on a substrate 108. The gate stacks 102, 106 are separated by a spacer gap 104. To prevent charge leakage, oxide spacers 110 are formed on each side of the gate stacks 102, 106. These oxide spacers are typically formed using a conventional high temperature chemical vapor deposition (CVD) methodology or a spin-on technique.
The CVD methodology is typically utilized because of its high quality (good thickness uniformity, high purity and density, high degree of structural perfection, etc.) However, as dimensions are reduced in each new generation of integrated circuit, it becomes more difficult to deposit oxide material utilizing the conventional high temperature CVD methodology. For example, as a result of the reduced dimensions, the spacer gaps are smaller (0.32 microns or lower), therefore the formation of voids during the CVD process becomes a more significant concern. Voids create weaknesses in the oxide spacers 110 which reduces the reliability of the device. Furthermore, utilizing a conventional spin-on methodology produces substantially void free oxide spacers, but conventional spin-on methodology is not utilized at the transistor device level.
Accordingly, what is needed is a method for eliminating voids in the oxide spacers of the spacer gaps of semiconductor devices while maintaining the high quality provided through the use of the CVD methodology. The present invention addresses such a need.
The present invention is a method and system for processing a semiconductor device, the semiconductor device comprising at least two gate stacks and a spacer gap. The method and system comprise utilizing a spin-on technique at the transistor device level to provide an oxide spacer in the spacer gap and then curing the semiconductor device at a temperature above approximately 450xc2x0 C.
Through the use of a system/method in accordance with the present invention, the voids that are created in the core spacer gaps during conventional semiconductor processing are eliminated. Furthermore, the oxide spacers possess the high quality characteristics that are typically provided through the use of the conventional CVD methodology. Accordingly, as a result of the use of the system/method in accordance with the present invention, the MOSFET oxide spacers are strengthened, which increases the reliability of the semiconductor device.